1. Field of the Invention
The present invention relates generally to electronic systems where accurate and stable signal edge placement is required. More particularly the present invention relates to a CMOS-NMOS programmable capacitance time vernier and a method for calibrating the same.
2. Related Art
Conventionally, manufacturers of test systems for integrated circuits have used bipolar technology to implement the timing control. However, high power solutions such as those implemented with bipolar technology limit the functionality as compared to a low power technology such as CMOS (Complementary Metal Oxide Semiconductor). Further, high power solutions often require the addition of water cooling in order to maintain a workable system environment.
Those skilled in the art understand that solutions utilizing CMOS technology rather than bipolar technology greatly reduce the system power requirement and may therefore obviate water cooling. CMOS technology offers more functionality at a greatly reduced power.
One aspect of test system development that the inventors are involved with is the design of vector formatters. A vector formatter generates coarse timing edges used for testing integrated circuits. The inventors previously designed a vector formatter that provides high performance specifications such as low skew specifications and low jitter specifications on the critical paths of the integrated circuit device.
Coarse timing edges, however, generally require some fine tuning. In a previous design, the output signal of the vector formatter is conventionally driven into a BT605 time vernier (Brooktree Corporation, San Diego, Calif.), which performs a fine time adjustment to skew (fine tune with respect to time) the input coarse edge. In contrast to the vector formatter which is implemented in CMOS technology, the Brooktree BT605 is implemented in bipolar technology, which has a high power requirement.
The bipolar solution is also limited in bandwidth due to the ramp-comparator technique. The ramp-comparator technique involves charging a capacitor with a constant current, and producing a voltage ramp, which is subsequently compared to a reference voltage with a comparator. The technique limits the bandwidth due to discharging the capacitor between edges. Because an N number of BT605 circuits are required, where N is the number of functional test pins times the number of data format types per edge, the power and space requirements of this circuit and its supporting circuitry are multiplied by N. Therefore, by eliminating the bipolar time vernier and integrating the vector formatter and time vernier functions on one silicon die, which is fabricated using CMOS technology, the resulting system would have greatly reduced power and space requirements. The challenge of designing such a system would be to design a time vernier using CMOS technology that would at least meet the performance of the conventional bipolar circuit. This task was a challenge since bipolar technology is usually considered to have higher bandwidth performance than CMOS technology.
Although some CMOS time vernier designs exist, that is adjusting coarse timing edges finely in time, performance with respect to skew and jitter were not sufficient. (See Branson et al.'s article titled "Integrated PIN Electronics for a VLSI Test System," IEEE International Test Conference, 1988 pp. 23-27.) These techniques involved multiple delay elements which were tapped or multiplexed to obtain the desired delay. A large look-up table RAM and redundant hardware elements were needed for calibration. However, with these existing CMOS circuits, skew and linearity performance were still not sufficient with respect to market requirements. Hence, previous CMOS integration of delay lines has only been used for lower performance systems. Bipolar subsystems which consume high power have been required to implement high performance fine timing generation.